Manufacturers of semiconductor chips often perform extensive testing of the functionality of each chip before shipping it to its customers. This is important to the customer, since the use of a bad chip may ruin a larger assembly. The testing may involve a number of different parameters and functions of the chip, such as pin timing parameters. Due to increasingly stringent specifications of pin timing, the testing of these parameters and functions is becoming more difficult and more involved, and may require the use of increasingly expensive testing equipment. In addition, as the bus speeds increase, it becomes increasingly difficult and expensive for testing equipment (built with prior generation (slower) chips) to test the faster functions of a newer generation (faster) chip. Further, when testing very short functions (such as those involving the input setup time of a signal), the time period necessary for testing may assume a large part of the entire test period. Accordingly, it would be helpful to be able to test the chip without resorting to external testing equipment, such as by performing internal tests, so that expensive testing equipment can be avoided or use thereof minimized, and so that newer generation chip speeds do not impact testing.
One concept useable in this regard is called I/O loop-back (IOLB) testing. In this arrangement, an output pad is connected to an output latch through a driver, and also connected to an input latch through a buffer, so as to form a loop-back path. In order to test the speed of the device, the time required to send the data out and receive it back via the loop-back path is determined. This also tests data integrity, i.e., whether the output latch and input latch correctly output and input the applied signals.
One such type of system was used in U.S. Pat. No. 5,621,739, which shows a method for a buffer self-test. The buffer circuit utilizes an adjustable delay circuit to test whether the buffer can capture a data value during a variable strobe window. A self-testing buffer circuit generates a data value, and a latch then receives such data value. An adjustable delay circuit provides an adjustably delayed strobe to a clock input of the latch. A comparison circuit compares the latch output value to an expected value. A failure is indicated when the value is not that which is expected.
While these kinds of systems avoid some of the previously noted problems, they still have not been completely successful in removing all of these problems. One of the unsolved problems is related to the use of different clock domains for generating test data and test strobe. As a result, the data and strobe can only be exercised in a single-shot, non-repetitive manner. To guarantee correct operation, the logic has to ensure proper alignment between the clocks that generate the test data and strobes. Running the test operation during clock misalignment may cause failures that are not the fault of the chip being tested. Thus, good chips may be thrown out as being defective, or the ability to test the device must be limited so that these errors are not introduced.